The present invention relates generally to fabrication of integrated circuits, and more particularly, to a method and apparatus for directly polishing an outer edge ring of a semiconductor wafer to prevent delamination of layers of material deposited on the outer edge ring of the semiconductor wafer during fabrication of integrated circuits thereon.
FIG. 1 shows a typical shape of a semiconductor wafer 102 having integrated circuits fabricated thereon, as known to one of ordinary skill in the art of integrated circuit fabrication. During fabrication of integrated circuits on the semiconductor wafer 102, various layers of material are deposited onto the semiconductor wafer 102 on top of one another, as known to one of ordinary skill in the art of integrated circuit fabrication. Such layers of material however may delaminate and peel-off away from near the outer edge 103 of the semiconductor wafer 102, as known to one of ordinary skill in the art of integrated circuit fabrication. Such peeling of material away from near the outer edge 103 of the semiconductor wafer 102 creates a source of contaminants for the rest of the semiconductor wafer 102 which may render the integrated circuits fabricated on the semiconductor wafer inoperative.
A factor which may promote this undesired delamination and peeling off of layers of material away from near the outer edge 103 of the semiconductor wafer 102 are clamps which hold the semiconductor wafer 102 near the outer edge 103 of the semiconductor wafer 102. The semiconductor wafer 102 is held by clamping mechanisms within various integrated circuit fabrication equipment near the outer edge 103 of the semiconductor wafer 102.
Referring to FIG. 2A for example, a clamping ring 104 may hold the semiconductor wafer 102 all around the outer edge of the semiconductor wafer 102. (The dashed circle in FIG. 2A represents the circumference of the semiconductor wafer 102 held by the clamping ring 104.) FIG. 2B is the cross-sectional view of the clamping ring 104 holding the semiconductor wafer 102 across line Ixe2x80x94I in FIG. 2A. Referring to FIG. 2B, the clamping ring 104 holds and covers an outer edge ring 106 all around the circumference of the semiconductor wafer 102.
Alternatively, referring to FIG. 3A, a plurality of clamping pins, including a first clamping pin 302, a second clamping pin 304, a third clamping pin 306, and a fourth clamping pin 308 holds the semiconductor wafer 102 at a plurality of positions near the outer edge of the semiconductor wafer 102. Typically, a higher number of clamping pins holds the semiconductor wafer 102 near the outer edge 103 of the semiconductor wafer 102, but four clamping pins 302, 304, 306, and 308 are shown in FIG. 3A for clarity of illustration. FIG. 3B is the cross-sectional view of the clamping pins 302 and 306 holding the semiconductor wafer 102 across line IIxe2x80x94II in FIG. 3A. Referring to FIG. 3B, the clamping pins 302 and 306 hold and cover an outer edge distance 310 of the semiconductor wafer 102.
When either of the clamping ring 104 of FIG. 2A or the clamping pins 302, 304, 306, and 308 of FIG. 3A holds the semiconductor wafer 102 during deposition of material on the semiconductor wafer, such material is not deposited near the outer edge of the semiconductor wafer 102 held by the clamping ring 104 or the clamping pins 302, 304, 306, and 308. The semiconductor wafer 102 moves through multiple integrated circuit fabrication equipments typically for deposition of numerous layers of material. Because of misalignment of the semiconductor wafer 102 at the various integrated circuit fabrication equipments, these layers of material may delaminate and peel-off away from near the edge of the semiconductor wafer.
Referring to FIG. 4 for example, a first layer of material 402 is deposited on the semiconductor wafer 102 at a first integrated circuit fabrication equipment, a second layer of material 404 is deposited at a second integrated circuit fabrication equipment, and a third layer of material 406 is deposited at a third integrated circuit fabrication equipment. At each of many of these different integrated circuit fabrication equipments, a clamping ring or a plurality of clamping pins should hold the semiconductor wafer 102 at an outer edge distance 408 inward from the outer edge 103 of the semiconductor wafer.
Such an outer edge distance 408 is typically on the order of 4 mm (millimeters). Because of such a short distance and because the many fabrication equipments lack fine wafer alignment capability with respect to the clamping ring or the plurality of clamping pins, the misalignment of the semiconductor wafer 104 through the multiple integrated circuit fabrication equipments results in various extensions of the layers of materials into the outer edge distance 408.
Referring to FIG. 4, for example, the first layer of material 402 extends outward toward the outer edge 103 of the semiconductor wafer 102 beyond the outer edge distance 408. The second layer of material 404 extends outward even further than the first layer of material 402 toward the outer edge 103 of the semiconductor wafer beyond the outer edge distance 408. The third layer of material 406 is misaligned such that the third layer of material 406 extends inward toward the center of the semiconductor wafer 102 away from the outer edge distance 408.
Because of such misalignment of the multiple layers of material 402, 404, and 406, any of such layer of material 402, 404, and 406 may delaminate and peel-off away from near the outer edge 103 of the semiconductor wafer 102, as known to one of ordinary skill in the art of integrated circuit fabrication. For example, referring to FIG. 4, the second layer of material 404 hangs over the first layer of material 402 and beyond the third layer of material 406. Thus, the second layer of material 404 is likely to peel-off away from the semiconductor wafer 102. Such delamination and peeling-off of the misaligned layers of material are especially likely when abutting layers of material do not have strong adhesion.
Such peeling of material away from the edge of the semiconductor wafer may render the integrated circuits thereon inoperative. In addition, such peeling of material away from near the outer edge 103 of the semiconductor wafer 102 creates a source of contaminants for the rest of the semiconductor wafer 102 which may render the integrated circuits fabricated thereon inoperative. Such peeling of material away from near the outer edge 103 of the semiconductor wafer 102 may also contaminate integrated circuit fabrication equipment chambers during subsequent process steps. In the prior art, when a layer of material begins to peel away from the semiconductor wafer, the semiconductor wafer is reworked to remove the layer of material that is peeling away. However, such reworking of the semiconductor wafer is relatively complicated and time-consuming or in some cases very difficult. Alternatively, such a semiconductor wafer is scrapped which is a waste. Thus, a mechanism is desired for polishing the misaligned layers of material near the outer edge of the semiconductor wafer to efficiently and effectively prevent the delamination and peeling-off of the layers of material away from the semiconductor wafer during fabrication of integrated circuits thereon.
Accordingly, in a general aspect of the present invention, in an apparatus and method for polishing an outer edge ring of a semiconductor wafer, the semiconductor wafer is mounted on a wafer chuck. The semiconductor wafer has layers of material deposited thereon during fabrication of integrated circuits on the semiconductor wafer. The wafer chuck holding the semiconductor wafer is rotated such that the semiconductor wafer rotates. A polishing pad is moved toward the semiconductor wafer as the semiconductor wafer is rotating. The polishing pad has a polishing surface that faces and contacts the outer edge ring of the semiconductor wafer as the polishing pad is moved toward the semiconductor wafer to polish the outer edge ring of the semiconductor wafer. The layers of material deposited on the outer edge ring of the semiconductor wafer is polished offby the polishing surface of the polishing pad.
The present invention may be used to particular advantage when the polishing surface of the polishing pad is tapered such that an upper portion of the polishing surface that is to contact an upper layer of material disposed further away from the semiconductor wafer extends further toward the semiconductor wafer such that the polishing surface forms a taper angle with respect to a plane of the semiconductor wafer. The taper angle may be in a range of from about 30xc2x0 to about 60xc2x0. Such a taper angle of the polishing pad ensures that the edge of an upper layer of material that is disposed further from the semiconductor wafer is disposed more inward toward the center of the semiconductor wafer such that the upper layer of material is not likely to delaminate and peel-off away from a lower abutting layer of material on the semiconductor wafer. The polishing surface may also be a rectangular shaped surface that faces and contacts a portion of the outer edge ring during polishing of the outer edge ring of the semiconductor wafer.
Furthermore, a photodetector may determine sufficient polishing of the outer edge ring of the semiconductor wafer. In that case, the polishing pad is moved away from the semiconductor wafer upon detection of sufficient polishing of the outer edge ring of the semiconductor wafer.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.